Description

Design Verification ensures that the RTL design functions as intended. With the increasing complexity of chips, robust verification is vital for first-pass silicon success. This course focuses on SystemVerilog, UVM, coverage, assertions, and real-world verification flows.

Curriculum

• Fundamentals of Functional Verification
• SystemVerilog for Verification
• Building Testbenches: Drivers, Monitors, Scoreboards
• Functional Coverage & Assertions (SVA)
• Universal Verification Methodology (UVM)
• UVM Sequences, Configuration, Callbacks, Factory
• Register Layer and DPI-C Integration
• Simulation with VCS/Questa
• Debugging: DVE, SimVision
• Case Study: SoC Verification Flow