Description

This course focuses on transforming RTL to gate-level netlist and analyzing timing to ensure performance goals are met. STA and synthesis are crucial for silicon accuracy and performance.

Curriculum

• RTL Design Guidelines for Synthesis
• Combinational and Sequential Logic Optimization
• Timing Constraints (SDC): Clocks, Exceptions
• Setup, Hold, Skew, Jitter, and Slack
• Multi-cycle and False Paths
• Clock Gating and Pipelining
• Netlist Analysis using Design Compiler
• Static Timing Analysis using PrimeTime
• Formal Equivalence Checking (Formality)
• Lab: Writing Constraints and STA Debugging