Description
DFT ensures chips can be tested efficiently post-fabrication. This course teaches scan insertion, ATPG, BIST, JTAG, and test compression to improve fault coverage and yield.
Curriculum
- Introduction to DFT and Fault Models
- Scan Chain Insertion and Stitching
- ATPG (Automatic Test Pattern Generation)
- Transition Fault and Delay Testing
- Memory BIST and Logic BIST
- JTAG and Boundary Scan (IEEE 1149.1)
- Test Compression Techniques
- Fault Simulation & Coverage Analysis
- DFT Tool Flow: Tessent, TetraMAX
- Debugging Scan and Test Failures
